The present invention relates to a method of fabricating a semiconductor device. In more particular, the present invention relates to a method of fabricating a semiconductor device with a high-degree of integration, and relates to a fine pattern formation method of separates interconnect pattern in devices such as transistors by using dimension control technique.
In recent years, there is a continuing trend of manufacturing semiconductor devices which are finer and finer and more and more integrated. This scaling-trend results in shorter gate lengths in MOS transistors mounted on LSI circuits and shorter distance and smaller pitch of mutually adjacent wirings. Similarly, also for memory cell such as of an SRAM mounted on LSI circuits, there is a demand for reduction in bit costs by increasing packing density. Therefore, resolution enhancement technique (RET) such as an alternative phase-shifting mask (e.g. Levenson phase shift mask) technology is used to meet the demand for size reduction. However, the changing of the demand for size reduction of the semiconductor device is faster than improvement of resolution in lithography. Therefore, instead of the resolution improvement in lithography, resist trimming process which decrease photoresist pattern size by isotropic dry-etching of patterned photoresist (e.g. for a gate electrode arranged in line-and-space) is in practical use to make fine patterns that is below the resolution limit of the current lithography. Japanese Patent Laid-Open No. 2004-103999 discloses a technology of forming a fine pattern for LSI circuit, by forming a first pattern and then forming a fine space pattern to become a second pattern through exposure and development. On the other hand, Japanese Patent Laid-Open No. 2005-166884 carries out processing on film to be processed with a space control film and a resist mask for forming a fine space superior to a space which the lithographic resolution technology attains.
Japanese Patent Laid-Open No. 2006-41364 discloses a method of forming wirings wherein an anti-reflective coating film is etched with gas consisted of CHF3, CF4 and O2. The document specifies that etching on an anti-reflective coating film with etching gas of CHF3:O2=1:1 to 9:1 enables etching without changing the pattern size.
Japanese Patent Laid-Open No. 2006-156657 discloses a technology of forming a fine pattern below resolution limit of lithography, by forming a first pattern on an electrically conductive film within lithography resolution and then trimming this first pattern by dry-etching. (FIG. 9)
Japanese Patent Laid-Open No. 2002-198362 and Japanese Patent Laid-Open No. 2002-141336 disclose a method of forming a contact hole by using mixing gas of O2 (etching agent) and added gas enhancing deposition such as CH2F2 or CHF3. In the document, it is described to adjust CH2F2 gas flow to control the diameter of the contact hole.
However, the present inventor has found out problems to be described below. Desired properties of semiconductor devices are unavailable since displacement takes place in a portion requiring overlapping between wiring pattern and its upper or lower conductor layer which is connecting to the wiring pattern when displacement in a second pattern occurs at the occasion of forming a wiring pattern by dividing the first pattern with the second pattern.